The world’s largest chip foundry, TSMC, is about to kick off mass production of cutting-edge chips using its 3nm process node. To put it in simple terms, as the process node number drops, the transistors used to build these integrated circuits become smaller allowing more of them to fit inside a small, dense space like a chip. And the higher a chip’s transistor count, the more powerful and energy-efficient it is.
The iPhone 15 Pro and iPhone 15 Ultra are expected to feature the 3nm A17 Bionic chipset
TSMC’s 3nm chips will continue to use FinFET transistors (at left) while Samsung’s 3nm chips will use GAA
This Thursday, TSMC is expected to mark the beginning of 3nm mass production by holding a ceremony at Fab 18 at the Southern Taiwan Science Park. At the event, TSMC will discuss its plans to expand 3nm production at that fab. The A17 Bionic and the M3 chip are both expected to ship later next year having been built using TSMC’s enhanced 3nm process node.
The only other foundry in the world able to mass produce at 3nm presently is Samsung Foundry. The latter uses gate-all-around (GAA) transistors which allow for more precise control of current flow through each transistor. This is accomplished by having the gates (which turn on and off to allow or block current flow) come into contact with the channels on all sides. With GAA, power efficiency is improved. Simply put, chips using GAA transistors run faster and consume less power than chips using FinFET transistors.
Samsung to use GAA transistors with its 3nm production; TSMC will continue with FinFET until it’s at 2nm production
So what’s coming after 3nm?
Helping with Intel’s quest to topple TSMC and Samsung Foundry, it will be the first foundry to own ASML’s next-generation Extreme Ultraviolet (EUV) lithography product, the High Numerical Aperture Extreme Ultraviolet Lithography machine. ASML is responsible for the production and sale of every EUV lithography machine on the planet.
The new lithography machines will allow foundries to etch circuitry designs at higher resolutions to enable 1.7x smaller chip features and 2.9x increased chip density. This will help Intel etch extremely thin circuity patterns on wafers allowing for the placement of billions of additional transistors to be placed inside a chip.
