Why do we phone enthusiasts go nuts every time a foundry moves to a new process node? The most basic response I can think of is that as the process node drops, so does the size of the transistors used in a chip. Smaller transistors mean that more of them can fit inside a chip increasing the transistor count and the higher a transistor count, the more powerful and/or energy-efficient a chip is.
By 2025, Intel, Samsung Foundry, and TSMC will all be using Gate-All-Around transistors
All three foundries will also use backside power delivery at 2nm (20A for Intel which calls its version Power Via). This moves all power connections from the top of the chip to the bottom allowing more room for the data interconnects above the silicon and helps create larger power connections on the bottom of the chip. This will also lead to improved chip performance.
