TSMC was charging chip designers $20,000 for each silicon wafer used to produce a 3nm chipset. Each wafer can produce 300 to 400 chips. At $30,000, the wafer used for 2nm production is 50% more expensive than the $20,000 TSMC charged for the wafer used in 3nm production. It is twice as expensive as the $15,000 charged for the wafers used in TSMC’s 4nm and 5nm production. Going back even more, in 2014 TSMC charged clients $3,000 for wafers used to build its 28nm chips.
The 2nm node will debut a couple of new features for chips built by TSMC. The foundry’s 2nm chips will use nanosheet Gate-all-around (GAA) transistors to replace FinFET. With GAA, the gate comes into contact with the channel on all sides reducing current leakage and improving the drive current. This results in a 10% to 15% power boost, a 15% transistor density increase, and a 25% to 30% reduction in power consumption.
TSMC’s 2nm production will also include backside power delivery (BPD) which moves the power connections to the back side of the chip allowing them to be shorter than the connections used with traditional frontside power delivery. This results in a reduction in power loss from line resistance. The bottom line is a 15%-20% improvement in power usage.
