Intel’s A18 chipset will be equivalent to 1.8nm and feature Gate-All-Around and Backside Power Delivery
Intel’s 18A chips will match TSMC and Samsung Foundry’s 2nm chips by using Gate-All-Around (GAA) transistors that use vertically placed horizontal nanosheets allowing the gate to come into contact with the channel on all four sides. This resulots in less current leakage and a larger drive current. Intel will also match TSMC and Samsung at 2nm by using backside power delivery with the 18A node.
FinFET transistor on the left, Gate-All-Around on the right
With backside power delivery, the back side of the silicon wafer used to build a chip will distribute power instead of using the front side which is the typical method. With backside power delivery, shorter, wider lines can deliver power with less resistance and there is less congestion than the current frontside power delivery method used.