As part of its Architecture Day, Intel spent a lot of time discussing its next generation PC microprocessor microarchitecture, Alder Lake, which marks a radical change for Intel. The question for us in the data center is will the design make its way to the server? If past is prologue, then yes, in time.
Alder Lake is due later this fall in three versions: desktop, mobile, and ultra portable. It will come with up to 16 cores and 24 threads and support for PCI Express 5 and DDR5 memory plus other features.
Here’s where it gets interesting. The desktop part with 16 cores is actually a split between eight performance cores—P-Cores—and eight efficiency cores—E-Cores. The mobile and ultra-mobile parts also use this dual-core design but with fewer cores. The P-Core is for compute tasks, while the E-Core is assigned background tasks like email syncing and antivirus checks. This is hardly a new idea. Arm has done this for years with its big.LITTLE core designs.
And instead of the usual dual threads per core, E-Cores have no threads. Intel is introducing a new technology called Thread Director, a thread scheduler that ensures high-priority operations are dealt with first so app data always gets fed to the P-Cores.
Thread Director lives up to its name by asking which task goes first and on which core type it should run on. Intel developed the Thread Director in conjunction with Microsoft, and it will be a Windows 11 technology.
This and more leads to claims of a 19% performance leap over the current generation of desktop products on the market. So that leads to the obvious question: Will this design come to Xeon? The core designs have always started on the client and moved to the server, so it seems logical.
Intel is non-committal. A rep for the company said it is focused on Sapphire Rapids, the third generation of Xeon Scalable due next year. Any Xeon that would feature Alder Lake technology would come in 2023 at the earliest.
Shane Rau, research vice president for compute semiconductors at IDC, sees Alder Lake being utilized in server processors for some workloads. “Whether it’s specifically under the Xeon brand, I can’t speak to that. But just the trend is to mix and match IP onto silicon or into package(s) according to the destined workload or use case. And I think within some server workloads, one could identify workloads that would go back and forth between a performance mode and a power-efficient mode,” he said.
Rau notes that there are 90 Xeon SKUs already, mostly variations of core counts, clock speeds and caches. So why not add another feature choice of high performance versus low performance?
It’s common to associate Xeon with servers, but the product line is rather broad. There are Xeons for desktop workstations or departmental tower servers, and on the other end of the spectrum there are Xeons designed for eight-socket servers.
Rau said the performance/efficiency core design could find its way into servers, workstations, or embedded IT systems. “I would say it’s more than just dependent on the success or failure of Alder Lake,” he said.
Copyright © 2021 IDG Communications, Inc.
