Xilinx has introduced its latest data-center accelerator, the Alveo U55C, which it says is its most powerful accelerator yet thanks to a memory change.
For the most part, the FPGA-powered Alveo U55C is similar to its predecessor, Alveo U280. But the U280 has 8GB of HBM2 memory and 16GB of DDR4 DRAM, while the U55C comes with 16GB of HBM2 memory, and no DDR4. HBM2 is considerably faster and more expensive than DDR4 memory.
By going to all HBM2 and removing the DDR4, Xilinx is able to increase performance and considerably reduce power and size. The Alveo U55C card is a single-slot full height, half length (FHHL) form factor vs. the full height, full length, dual width form of the U280. It also has a much lower power draw, 150W vs. 215W.
The smaller form factor provides more compute density in the same space, suitable for creating dense Alveo accelerator-based clusters. It’s built for high-density streaming data, high I/O math, and scale-out applications like big-data analytics and AI.
“We’re shifting the position of Alveo in the data center,” Nathan Chang, HPC product manager at Xilinx said, “and it’s not just for niche architectures, or very specific data problems anymore. The goal is to create denser Alveo clusters, scaling out to target HPC workloads. That’s why we built this card.”
The U55C offers support for RDMA over Converged Ethernet (RoCE) v2 and message-passing interface (MPI) integration. HPC app developers can use the Xilinx Vitis software platform to build scale-out applications that span multiple Alveo cards, regardless of the server platforms and network infrastructure being used.
Xilinx says that the RoCE v2, 200Gbps bandwidth, and Vitis API-driven clustering enables an Alveo network to compete with InfiniBand in performance and latency with no network-vendor lock-in. Vitis platform and tools make the hardware more accessible to software developers and data scientists without requiring hardware expertise. Vitis supports major AI frameworks like Pytorch and Tensorflow as well as high-level programming languages like C, C++, and Python.
As part of the briefing, Chang talked about an HPC customer use case, Australia’s national science agency, CSIRO, and the Square Kilometre Array (SKA) Observatory of 131,000 radio antennas it is building. A cluster of 420 Alveo U55C cards does real-time signal processing of data gathered from the antennas, with an overall throughput of 15Tbs.
By scaling out across multiple Alveo U55C cards, performance with the SKA tools increased five-fold over x86 CPUs, while requiring half the number of servers and less than half the power compared to commodity GPUs, according to Xilinx.
The Xilinx Alveo U55C is available through the company’s website or Xilinx authorized distributors. It will also be available via public-cloud-based FPGA-as-a-service providers for remote evaluation, as well as through select colocation data centers for private previews. General availability isn’t expected until the second quarter of next year.
Copyright © 2021 IDG Communications, Inc.
